Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM  describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.
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Description of Related Art Recently, there has been increasing research on the buried word line cell array transistor BCAT in which a word line WL may be buried below the surface of a semiconductor substrate using a metal and not a polysilicon as a gate electrode in the structure of a conventional recess channel array transistor RCAT.
The capping layer may be formed of an insulating material e.
Example embodiments are defined by the following claims, with equivalents of the claims to be included therein. In example embodiments, forming the upper buried word line may include forming a second word line layer on the substrate so as to bury the trench in which the lower buried worrdline line may be formed, polishing the second word line layer using chemical mechanical polishing to expose the surface of the substrate, and recessing the polished second word line layer into the wkrdline to form the upper buried word line.
In example embodiments, the gate insulating layer may be a thermal oxide layer formed by thermal oxidation. The lower buried word line may be formed by forming a first word line layer not shown on the substrate so as to bury the trench In addition, a description of forming layers within and on the gate using deposition and etching buries is also well known to those skilled in the art, and thus, omitted.
Unlike a polysilicon gate in a conventional DRAM, a word line having 0. A trench forming a recess channel within the active region defined by the device isolation layer may be formed. Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments and intermediate structures.
In example embodiments, the lower buried word line may include polysilicon. The word line layer may then be polished using a chemical mechanical polishing CMP method and etched back using a dry etch process to expose the surface of the substrate In the drawings, the thicknesses of layers and regions are exaggerated for qordline.
A method of fabricating a semiconductor device having a buried word line structure may comprise forming a device isolation layer defining an active region in a semiconductor substrate, forming a trench for forming one or more recess channels in the active region, forming a gate insulating layer on the surface of the trench, forming a gate electrode layer on the surface of the gate insulating layer, and forming a buried word line burying the trench on the surface of the gate electrode layer.
Burid top surfaces of the gate insulating layerthe gate electrode layerand the buried word line formed on the gate electrode layer may be formed so as to not protrude beyond the top surface of the substratee. Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same.
6F2 buried wordline DRAM cell for 40nm and beyond
Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. The trench may be formed so as to have a width within a range of about 10 to about nm, for example, below 50 nm.
And they are in volume production, we have also found them in a point and shoot camera. Elpida has also licensed the process, so given the cost and performance advantages, we can likely look forward to BwL product from Japan; and who knows what other manufacturers might go that way? Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. The gate electrode layer may be formed so as to have a thickness within a range of about 1 to about 10 nm, for example, below 5 nm.
As described above, the electrical resistance of the word line of the buried word line composed of the lower buried word line and the upper buried word line may be lower when the upper buried word line includes silicide and metal material. The gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method.
For example, in order to secure a step coverage above The semiconductor device of claim 1wherein the lower buried word line includes polysilicon.
This result may be related to the degradation of the reliability of the semiconductor device. Year of fee payment: The buried word line may comprise a lower buried word line formed in the lower region of the gate electrode layer, and an upper buried word line formed in eordline upper region of the gate electrode layer.
Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. In example embodiments, the trench may be formed to have a width within a range of about 10 to about nm.
Alternatively, the gate electrode layer may be recessed together with the second word line layer.
The upper buried word line may comprise a silicide. Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof. The semiconductor device having the buried metal gate electrode structure having a low resistance and a method of manufacturing the same.
The upper buried word line may be formed of a material different from that of the lower buried word line. The upper buried word line may be formed by forming a second word line layer not shown on the substrate so as to bury the trench including the lower buried word line The upper buried word line may be formed of a silicide e.
M Year of fee payment: In example embodiments, the buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition ALD method.
Semiconductor integrated circuit device capable of securing gate performance and channel length. In addition, in the semiconductor device according to example embodiments, the gate electrode may be formed of a different material from that of the word line.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
6F2 buried wordline DRAM cell for 40nm and beyond – Semantic Scholar
In example embodiments, the gate electrode layer may be formed using a chemical vapor deposition CVD or an atomic layer deposition ALD method. One other point was made by Qimonda before they went under, that this technology is particularly suitable for a cell shrink from the current 6F2 to a 4F2 format, enabling even more cost savings by reducing die size.
A semiconductor device having a buried word line structure, comprising: Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which wkrdline embodiments belong.
The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising wordlind active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line bhried which the trench may be buried on the surface of the gate electrode layer. The second word line layer may then be polished using chemical mechanical polishing to expose the surface of the substrate Extension Media websites place cookies on your device to give you the best user experience.
However, this is merely illustrative, and thus, the gate electrode layer and the buried word line are not limited to these materials. As such, the degradation of the oxide layer, which may be caused by the formation of the titanium nitride layer, may be reduced or prevented.